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! ' '" %# $$ prepared by: rick honda and scott deuty motorola, inc. introduction this paper will describe an easy method to analyze perfor- mance of various power mosfets in step down switching regulators using the pspice circuit analysis tool. a compari- son will be made between circuit simulation results and the measured performance described in motorola application note an1520. the utility of having a model which closely simulates switch- ing performance is that different mosfets and diodes can be used in the model and comparisons can be made for proper performance vs. price, size, etc. prior to building breadboards. actual hardware should always be used to verify perfor- mance, but a good simulation model gives the designer a means of trying various combinations of parts quickly to see how well they work in a particular circuit. the motorola semiconductor components website has spice, pspice, hspice, and saber models available to down- load for numerous nchannel and pchannel mosfets along with several power rectifiers. application note an1520 [1] can be found at www.motsps.com/books/apnotes. it should be noted that a full version of pspice is needed to run these simulations, the numerous demo versions do not support the complexity of the mosfet models. a copy of the pspice circuit model listing is included for reference. circuit description the circuit described in an1520 is a 5 v to 3.3 v output buck regulator using synchronous rectifiers. the paper gives an overview on the operation of a buck regulator and the various waveforms through the power components. also included in the application note are actual measurements of waveforms and power dissipations. figure 1 shows a block diagram of the circuit configuration. a schematic of the circuit is shown in figure 2. dc input q2 p-channel d1 parallel schottky q1 n-channel control i c u1 c out l buck r load + figure 1. typical buck regulator employing a synchronous rectifier (source: motorola application note an1520) order this document by an1631/d semiconductor application note ? motorola, inc. 1998
2 motorola shutdown taje227k004 taje227k004 taje227k004 220 m f avx c1 c2 c3 r4 d2 u1 r3 10 k w 1% q1 hdtmos q2 hdtmos 1 13 14 8 7 9 10 4 6 5 c4 220 pf 6.04 k w 1% c8 0.1 m f c5 0.1 m f c7 3300 pf r2 0.05 w irc 2010-r050j 220 m f avx 220 m f avx l1 62 m h coiltronics ctx 62-2-mp +v out c6 330 pf +5 v v fb shutdown c i th i nt pgnd nc sgn ltc1148 n pgate ngate sense+ sense r1 510 w 12 2 11 3 v out 3.3 vdc v in c t 390 pf figure 2. physical circuit schematic of a 5 vdc to 3.3 vdc buck converter employing a synchronous rectifier (source: motorola application note an1520) the pspice model (figure 3) follows the power stages of the circuit very closely. the model was set up to operate in an open loop configuration since the switching characteristics of the main switching transistor, synchronous rectifier, and flyback diode were of most interest. the duty cycle of the power switch vout/vin or 3.3 v/5 v = 66%. an lc input filter was added for simulation purposes to smooth the input current to the regulator to facilitate measurements for efficiency calculations. figure 3. pspice schematic of a 5 vdc to 3.3 vdc buck converter employing a synchronous rectifier lin 1e06h rin 0.001 vin 5 v w cin 2e05f recin 0.001 w cmp 8e05f rdm 0.22 w vin rc_qpdrive 4700 w qp_source qmod1 810 mmsf3p02 mmsf3p02 qn_source qmod1 vmon_syncrect lbuck 6e05h rlbuck 0.02 w cres_lbuck 4e10f 3 rsen 0.05 w c1 0.00022f rec1 0.1 w c3 0.00022f rec3 0.1 w c2 0.00022f rec2 0.1 w rload 3.3 w vmon_buck o m v dflyback mbrs14013 mmsf5n03 qp_sink qmod1 rb_qpsink 1000 w qp_drive qmod1 rb_qpdrive 1000 w vdr_pgate 50000 hz/67% since 0v + + rc_qndrive 4.7 k w 600 qn_sink qmod1 rb_qnsink 1000 w + rb_qndrive 1000 w qn_drive qmod1 vdr_ngate 50000 hz/75% o m v
3 motorola figure 4. pspice schematic of the n channel mosfet model 10 core mosfet ldrain 11 rdrain1 4 5 6 6 31 30 8 rdbody dbody rdrain2 2 dgd 3 cgd rgd 21 20 lgate cgs rsource lsource a simple totem pole driver was included in the model to simulate the output driver stages of the ltc1148. the dead time of the switches was picked up from the measurements in the app. notes. for most pulse width modulators, the dead time can be calculated from the value of the timing capacitor. closed loop characteristics such as loop response and dc regulation can also be analyzed in pspice using the state space models described in many other papers. pspice modeling details it is important to check any downloaded spice models for accuracy to the component data sheets. for diodes, a dc sweep of current through the diode vs. voltage drop should be run to verify that the model matches the data sheet. for mosfets, the switching time test set up can be copied from the data sheet and a simulation run to see if the switching time and on resistance matches the measured values. it is important to run any mosfet models in a simple switching circuit before putting them into a more complex one. some mosfet models have convergence problems when running time domain analysis. the model was run in the time domain for many cycles (800 m s at a switching period of 20 m s in 20ns steps). this was done to allow the transients to settle out. options were set up in the transient analysis statement to bypass an initial dc operating point which pspice defaults to and instead use the specified initial conditions. the input voltage to the power switch was set to 5 v and the output voltage was set to 3.3 v. the initial condition on the output voltage puts an initial charge on the output capacitors. this greatly decreases the simula- tion time needed to reach a steady state condition since the capacitors do not have to charge up from 0 v. it is also impor- tant to use the itl5 = 0 option which increases the number of iterations allowed during transient analysis. this is needed since many iterations are required during the switching transi- tions of the power devices. since the mosfet models are set up as subcircuits con- taining numerous components, it can be difficult to see the total current into the drain or from the source. for modeling purposes, 0v voltage sources were placed in series with mosfets to monitor the current. in spice, voltage sources have zero resistance and thus do not affect circuit operation. this model was also run using hspice (96.3.1) on a unix workstation with simulation times on the order of 5 minutes. the results from pspice and hspice were very similar. the particular version of pspice used did not have very good graphical capability to view the simulation results. the results from the simulations were loaded into excel, parsed, and graphed for inclusion into this document. more advanced versions of pspice have improved graphics, front end sche- matic entry, and various other useful features. excel was also used to calculate average values of input current and output voltage for efficiency calculations. the components in the output lc filter included extra com- ponents to account for nonideal elements. the power induc- tor was composed of a series resistor with the inductor to account for winding resistance. a capacitor was placed in parallel with the series lc to account for the inductor self resonance. the output capacitors included series resistors to
4 motorola simulate equivalent series resistance. these elements help the switching waveforms in the model to show nonideal results such as current and voltage spikes. the load current was set to 1a for the analyses showing the waveforms. pspice modeling results figure 5 shows the current waveform of the main switching transistor as calculated by the circuit model. the various dif- ferent mosfets used in application note an1520 were all run in the model with similar results. the mosfets used were: pchannel (main power switch): mmsf3p02 nchannel (synchronous rectifier): mms5n03hd, mms3n03hd schottky diode: mbr140 note: no models were available for the mmdf2p02hd, mmdf2c02e, and mmdf2c02e mosfets also referenced in application note an1520. main switch transistor current 5.00e01 0.00e+00 5.00e01 1.00e+00 1.50e+00 2.00e+00 5us/div iq figure 5. pspice waveform of the current through the main, p channel, switching transistors (mmsf3p02 in figure 2) analysis of the waveforms synchronous rectifier and flyback diode current 1.00e+00 5.00e01 0.00e+00 5.00e01 1.00e+00 1.50e+00 5us/div isr id figure 6. pspice waveform of the synchronous rectifier transistor and the flyback diode (mms5n03hd transistors and mbr140 schottky diodes respectively in figure 2)
5 motorola figure 7 shows an expanded view of the current in the synchronous rectifier leg and is very similar to figure 8 that measured the performance of the physical circuit in the origi- nal application note. synchronous rectifier and parallel schottky current dead time trr 8.00e01 6.00e01 4.00e01 2.00e01 0.00e+00 2.00e01 4.00e01 6.00e01 8.00e01 1.00e+00 1.20e+00 1.40e+00 2 s/div isr id figure 7. shows an expanded view of the spice waveform (note the similarity to the physical circuit) time ( m sec) 012345 1.2 1 0.8 0.6 0.4 0.2 0.2 0 0.4 0.6 i d of sr transistor schottky current current (amperes) figure 8. waveforms of synchronous rectifier transistor drain current and parallel schottky current (i out = 1 amp) from the physical circuit
6 motorola figure 9 shows the expanded, leading edge of the current through the synchronous rectifier leg of the circuit. notice that the schottky takes the full current during the dead time and no body diode current is present. this is expected as the schottky has a lower forward voltage drop. however, it was shown in the physical circuit of figure 8 that the body diode does conduct current. similarly, the trailing edge of this current in figure 10 does not show any current in the schottky. these findings indicate that the spice model is not matching the measurements from the physical circuit in terms of interaction of current interaction between syncronous rectifier transistor and parallel schottky. figure 9. expanded leading edge current (no inductance in schottky path) figure 10. expanded trailing edge current (no inductance in schottky path) 774.2 1.5 0.5 1.0 0 0.5 1.0 774.4 774.6 774.8 775.0 775.2 i(vmon_syncrect) sr transistor i(dflyback) schottky diode 779.9 1.5 0.5 1.0 0 0.5 1.0 780.1 780.15 780.2 780.25 i(vmon_syncrect) sr transistor i(dflyback) schottky diode 779.95 780 780.05 schottky does turn on for a short period in spice analysis expanded leading edge of current in sync rec transistor and schottky expanded trailing edge of current in sync rec transistor and schottky a review of the spice model for the mbr140 diode reveals that no package inductance is listed. to account for the pack- age and board inductance, an exaggerated value of 50 nh was inserted in series with the mbr140 schottky and the model was run. the results of this test shown in figure 11 show that the body diode now biases up for a short period on the leading edge of the current waveform. figure 11. expanded leading edge current (50 nh inductance in schottky path) figure 12. expanded trailing edge current (50 nh inductance in schottky path) 774.2 1.5 0.5 1.0 0 0.5 1.0 775 775.2 775.4 i(vmon_syncrect) sr transistor i(dflyback) schottky diode 774.4 774.6 774.8 774.2 1.5 0.5 1.0 0 0.5 1.0 775 775.2 775.4 i(vmon_syncrect) sr transistor i(dflyback) schottky diode 774.4 774.6 774.8 expanded leading edge current in sync rec transistor and schottky with 50 nh of inductance in schottky leg expanded trailing edge current in sync rec transistor and schottky with 50 nh of inductance in schottky leg
7 motorola from the physical circuit and spice analysis it can be con- cluded that parasitics determine how the schottky improves circuit performance. an1520 argues the case for low rds(on) and its effects on circuit efficiency. however, work remains to be done on the interaction between the body diode of the synchronous rectifier transistor and the parallel schottky. the reverse recovery current of the body diode causes heating of the device and results in increased rds(on). this in turn effects circuit performance. by understanding the interaction between the body diode and parallel schottky, a more efficient design will result. the key is to design a system that uses the lower forward drop and faster recovery of the schottky. the power converter efficiency is simply pout/pin. this was calculated using excel by finding the average value of the output voltage and the average value of the current through an input current sense resistor. the efficiency is: eff vout 2 rload pr in rin (5 v) newer versions of pspice may allow direct measurement of the currents which will greatly ease efficiency calculations. the version of hspice used had this feature. efficiency was calculated for two load conditions (0.5a and 1a) using two of the combinations listed in figure 12 and table 3 of the application note an1520. the results are listed below: pchannel part no. nchannel part no. load current efficiency mmsf3p02hd mmsf5n03hd 0.5a 92.8% mmsf3p02hd mmsf5n03hd 1a 86.4% mmsf3p02hd mmdf3n03hd 0.5a 92.4% mmsf3p02hd mmdf3n03hd 1a 86.0% there is strong correlation of the efficiency values at 0.5a load, while the model indicates a slightly lower efficiency at a 1a load. the model does show the decrease in efficiency using the mmdf3n03hd mosfet vs. the mmsf5n03hd mosfet for the synchronous rectifier. the model can also be run without a synchronous rectifier and just the parallel schottky diode with its corresponding decrease in efficiency. thus the designer can simulate performance effectively with modeling and optimize the system prior to performing any physical layout. this correlation is important to the choice of schottky used. newer 5 to 3.3 v synchronous rectifier converters designed specifically for supplying intel processors have resulted in a new synchronous rectifier controller, the MC33470 from motorola, and a new hdtmos iii technology the mmsf3300 n channel mosfet. this design (figure 13) is highly opti- mized to achieve high efficiency at 300 khz (figure 14). no spice models were available at time of print however they are needed to understand the board. it has proven very difficult to breakout paths to measure the current in the synchronous rectifier leg and modeling could be a solution for further perfor- mance optimization.
8 motorola figure 13. the MC33470 based pentium ? design schematic digitally programmed reference oscillator c18 0.01 f + c11 680 f 4.0 v d2 l1 1.5 f q3 mmsf3300r2 q4 mmsf3300r2 mbrb1545ct c10 680 f 4.0 v c13 1.0 f c1 220 f 6.0 v c2 220 f 6.0 v ++ c6 1.0 f + over temp vid0 vid1 vid2 vid3 vid4 v cc + + + + voltage identification code input ot 64 ma 20 a + 18 17 16 15 14 9 6 r3 100 k to p j1b9 v ref 800 sense 11 v ref outen up# j1b6 d1 j1b5 19 5 r1 4.7 k c5 47 pf l2 1.5 h input voltage v in 5.0 v j 1a1, a2, a3, b1, b2 undervoltage lockout r10 51 c3 1.0 f 7 + agnd 4 10 + r5 1.2 k 100 pf c17 0.01 f r2 10 k delay r s q + r6 100 k 1.04 v ref pwr gd s r q fault indicate fault delay 0.96 v ref 12 r7 4.7 v ss r9 10 + ota error amp 13 pwm latch j1a7 j1b7 j1a8 j1b8 j1a9 comp c16 1.14 v ref j1a11, a13, a15, a17, a19, b10, b12, b14, b16, b18, b20 u1 2, 3 4 5, 6, 7, 8 2, 3 4 5, 6, 7, 8 2, 3 4 5, 6, 7, 8 2, 3 4 5, 6, 7, 8 3 1 8 20 2 g1 g2 i fb p gnd v drive q2 mmsf3300r2 q1 mmsf3300r2 r8 4.7 r4 56 v o 0.3 to 14 a j1a10, a12, a14, a16, a18, a20, b11, b13, b15, b17, b19 +12 v j1a4, b4 v cc v cc i max + outen ss 10 a v ref /2 0.96 v ref pwm comparator over current detect 1.5 v 2.5 v en 190 a 90 a 4.2/4.0 + + + 1.04 v ref
9 motorola 0 96% 92% 93% 91% 90% 89% 45 mbrb1035cl schottky efficiency no schottky efficiency with mbr1545d2pak 123 94% 95% 610 789 1112 figure 14. the MC33470 based pentium ? design efficiency summary the pspice and hspice circuit simulators are powerful tools which enable the designer to assess the effects of differ- ent devices in a power converter circuit using time domain analysis. this paper showed that the waveforms of a mea- sured breadboard can be modeled with strong correlation using a relatively simple circuit model along with available component models. some gaps in modeling were shown to exist. these gaps need to be overcome as more demand is placed on synchro- nous rectifier circuits to provide even lower logic level volt- ages reliably. references [1] ahdtmos power mosfets excel in synchr onous rectifier applications,'' deuty, motorola application note an1520, motorola literature distribution, p.o. box 5405, denver, colorado 80217.
10 motorola pspice program listing: ******* 07/08/97 ******* pspice 4.01 jan 1989 ******* 19:45:07 ******* motorola 5v3.3v buck regulator model **** circuit description **************************************************************************** * input voltage vin vin1 0 dc 5.0v rin vin1 vin4 .001 * * input filter (used to smooth out input current waveform) lin vin4 vin 1uh cin vin vin2 20uf recin vin2 0 .001 cmp vin vin3 80uf rdm vin3 0 .22 ****************************************** * flyback diode model (schottky diode) .model mbrs140t3 d is= 4.41547e06 rs= 0.103922 n= 1.03751 tt= 1e12 cjo= 1.598e10 vj= 0.4934 + m= 0.4258 eg= 0.6 xti= 3.29768 fc= 0.5 bv= 48 ibv= 0.01 kf= 0 af= 1 ***************************************** * synchronous recitifer model (nchannel mosfet) ***** microsim pspice(tm) simulators *********************** ************************** instantiation ******************* .subckt mmsf5n03hdp 10 20 30 * * 10 = drain 20 = gate 30 = source * *************************************************************** * * external parasitics * package inductance * ldrain 10 11 7.5e09 lgate 20 21 4.5e09 lsource 30 31 4.5e09 * * resistances * rdrain1 4 11 rdrain 0.02556 rdrain2 4 5 rdrain 0.001 rsource 31 6 rsource 0.01518 rdbody 8 30 rdbody 0.03772 * rgate 21 2 5 * * * * capacitances and body diode * dbody 8 11 dbody dgd 3 11 dgd cgdmax 2 3 2.3e09 rgdmax 2 3 1e+08 cgs 2 6 1.182e09 * * * * core mosfet * m1 5 2 6 6 main * * * .model rdrain res (tc1 = 0.01064 tc2 = 6.14682e06) * .model rsource res (tc1 = 0.009967 tc2 = 2.36438e05) * .model rdbody res (tc1 = 0.001953 tc2 = 6.62384e06) * * .model main nmos ( level= 3 vto = 2.359 kp = 22.07 gamma = 1.5 phi = 0.6 +lambda= 0.001 rd = 0 rs= 0 cbd= 0 cbs= 0 is = 1e14 pb= 0.8 cgso = 0 +cgdo = 0 cgbo = 0 rsh = 0 cj = 0 mj= 0.5 cjsw= 0 mjsw = 0.33 js= 1e14 +tox = 1e07 nsub = 1e+15 nss = 0 nfs = 2e+11 tpg = 1 xj = 0 ld= 0 uo = 600 +ucrit = 0 uexp= 0 utra = 0 vmax= 0 neff= 1 kf= 0 af= 1 fc= 0.5 delta= 0 +theta = 0 eta= 0 kappa = 0.2) *
11 motorola * * .model dgd d ( is = 1e15 rs = 0 n = 1000 tt = 0 cjo= 8.633e10 vj = 0.1 m = 0.487 +eg = 1.11 xti= 3 kf = 0 af = 1 fc = 0.5 bv = 10000 ibv= 0.001) * * * .model dbody d ( is= 1.668e12 rs = 0 n= 1.018 tt = 5e09 cjo= 1.2e09 vj= 0.5302 +m = 0.3689 eg = 1.11 xti = 4 kf = 0 af = 1 fc = 0.5 bv= 45.91 ibv= 0.00025) .ends * ******************************************************************* * power switch model (pchannel mosfet) .subckt mmsf3p02hdp 10 20 30 * * 10 = drain 20 = gate 30 = source * ******************************************************************* * * external parasitics * package inductance * ldrain 10 11 7.5e09 lgate 20 21 4.5e09 lsource 30 31 4.5e09 * * resistances * rdrain1 4 11 rdrain 0.04938 rdrain2 4 5 rdrain 0.001 rsource 31 6 rsource 0.01649 rdbody 8 30 rdbody 0.166 * rgate 21 2 5 * * * * capacitances and body diode * dbody 11 8 dbody dgd 11 3 dgd cgdmax 2 3 4.5e09 rgdmax 2 3 1e+08 cgs 2 6 9e10 * * * * core mosfet * m1 5 2 6 6 main * * * .model rdrain res ( tc1 = 0.003993 tc2 = 4.21478e05) * .model rsource res ( tc1 = 0.0055 tc2 = 1.73763e05) * .model rdbody res ( tc1 = 0.01634 tc2= 0.00019925) * * .model main pmos ( level = 3 vto = 2.194 kp = 14.71 gamma = 0.8 phi = 0.6 +lambda = 0.001 rd = 0 rs= 0 cbd = 0 cbs= 0 is= 1e14 pb = 0.8 cgso= 0 +cgdo = 0 cgbo = 0 rsh = 0 cj = 0 mj = 0.5 cjsw = 0 mjsw = 0.33 js= 1e14 +tox = 1e07 nsub = 1e+15 nss = 0 nfs = 2.5e+11 tpg = 1 xj = 0 ld = 0 uo = 600 +ucrit = 0 uexp = 0 utra = 0 vmax = 0 neff = 1 kf = 0 af = 1 fc = 0.5 delta = 0 +theta = 0 eta = 5000 kappa = 0.2) * * * .model dgd d ( is = 1e15 rs = 0 n = 1000 tt = 0 cjo= 1.891e09 vj= 0.3367 +m = 0.4348 eg = 1.11 xti = 3 kf = 0 af = 1 fc = 0.5 bv = 10000 ibv = 0.001) * * * .model dbody d ( is = 1.533e12 rs = 0 n = 1.029 tt = 1e12 cjo = 1.571e09 +vj = 0.7699 m = 0.3859 eg = 1.11 xti = 4 kf = 0 af = 1 fc = 0.5 bv = 28.91 +ibv = 0.00025) .ends
12 motorola ************************************************ * * buck switch (pchannel), parallel transistors in same package * subcircuit call xbuck_sw1 11 810 vin mmsf3p02hdp xbuck_sw2 11 810 vin mmsf3p02hdp * * 0v voltage source used to monitor currents through both switches vmon_buck 11 1 dc 0v **************************************************** * synchronous rectifier (nchannel) * subcircuit call xsync_rect 10 600 0 mmsf5n03hdp * * 0v voltage source used to monitor current through synchronous rectifier vmon_syncrect 10 1 dc 0v * ************************************************** * driver circuit for mosfets * power switch gate driver qp_source vin 100 810 qmod1 .model qmod1 npn bf=100 qp_sink 810 101 0 qmod1 qp_drive 100 102 0 qmod1 rc_qpdrive 100 vin 4.7k rb_qpdrive 102 103 1k rb_qpsink 101 103 1k * * drive to power switch: 50khz, 67% duty cycle, and dead time vdr_pgate 103 0 pulse(0v 5 0 .02us .02us 13.5us 20us) * * * synchronous rectifier gate driver qn_source vin 200 600 qmod1 qn_sink 600 201 0 qmod1 qn_drive 200 202 0 qmod1 rc_qndrive 200 vin 4.7k rb_qndrive 202 203 1k rb_qnsink 201 203 1k * * drive to synchcronous rectifier: 50khz, 25% duty cycle, and dead time vdr_ngate 203 0 pulse(0 5 0us .01us .01us 15.0us 20us) * set vdr_ngate to 5v dc to operate without synchronous restifier * ************************************************** * flyback diode dflyback 0 1 mbrs140t3 * ************************************************** * output filter * * output inductor and parasitics lbuck 1 2 60uh rlbuck 2 3 .02 cres_lbuck 1 3 400pf * * current sense resistor rsen 3 500 .05 * * output capacitors and esr c1 500 4 220uf rec1 4 0 .1 c2 500 5 220uf rec2 5 0 .1 c3 500 6 220uf rec3 6 0 .1 * * load resistor * node 500 is the output voltage rload 500 0 3.3 *
13 motorola ********************************************* * pspice option statements * itl5=0 allows unlimited number of iterations at each point in transient analysis .option nomod itl5=0 * * probe statements allow the points to be viewed graphically .probe i(vmon_buck) *.probe v(600) *.probe v(810) .probe i(vmon_syncrect) *.probe i(dflyback) .probe v(500) .probe i(rin) *.probe v(103) *.probe v(203) * * transient analysis control statement: * perform analysis out to 800us in 20ns steps, print out results starting at 760us * use initial conditions, do not calculate initial dc operating point .tran 20ns 800us 760us uic * * initial condition statements: sets output voltage to 3.3v and input to power switch to 5v .ic v(500)=3.3 v(vin)=5 * * print statements cause voltage, currents data points to be printed out * .print tran v(1) * .print tran i(lbuck) .print tran i(vmon_syncrect) .print tran i(vmon_buck) .print tran i(rin) .print tran i(dflyback) .end
14 motorola motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 4321 nishigotanda, shagawaku, tokyo, japan. 0354878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/ an1631/d ?

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